By Graham Birtwistle, Alan Davis
As the prices of energy and timing develop into more and more tough to control in conventional synchronous structures, designers are being compelled to examine asynchronous possible choices. in response to remodeled and increased papers from the VII Banff greater Order Workshop, this quantity examines asynchronous tools that have been utilized in huge circuit layout, starting from preliminary formal specification to extra usual finite kingdom computer established keep an eye on versions. Written by way of top practitioners within the quarter, the papers conceal many points of present perform together with functional layout, silicon compilation, and purposes of formal specification. it is also a cutting-edge survey of asynchronous layout. The ensuing quantity may be worthwhile to somebody attracted to designing right asynchronous circuits which convey excessive functionality or low energy operation.
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Additional resources for Asynchronous Digital Circuit Design
Each circle represents a handshake process or component. Each arc represents a channel, which connects an active port (indicated by a black dot) to a passive port (indicated by a white dot). Communication on a channel is by 29 a b Figure 16: Handshake circuit for BUFI example handshaking: an active port initiates a request and a passive port returns an acknowledgment. In this example, port [> is the top-level port for the circuit, called go. The environment activates the buffer by an initial request on this passive port.
Dill also introduced a theory of complete trace structures , based on Buchi automata, which can model general liveness properties. Although these general verification algorithms may be too expensive to apply in practice, a verifier has been developed for a constrained class of specifications . Other methods use a restricted notion of liveness that can be easily checked [47, 55]. An alternative verification method based on CCS has been proposed by Birtwistle, Stevens, et aZ. [123, 122].
A. Tapia. Synthesis of asynchronous sequential systems using boolean calculus. In 14th Asilomar Conference on Circuits, Systems and Computers, pages 205-209, November 1980. H. Tracey. Internal state assignments for asynchronous sequential machines. IEEE Transactions on Electronic Computers, EC-15:551-560, August 1966. T. Udding. A formal model for defining and classifying delay-insensitive circuits and systems. Distributed Computing, 1(4):197-204,1986. H. Unger. Asynchronous Sequential Switching Circuits.
Asynchronous Digital Circuit Design by Graham Birtwistle, Alan Davis